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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1995 jun 19 integrated circuits tda9850 i 2 c-bus controlled btsc stereo/sap decoder
1995 jun 19 2 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 features quasi alignment-free application due to automatic adjustment of channel separation via i 2 c-bus dbx noise reduction circuit dbx decoded stereo, second audio program (sap) or mono selectable at the af outputs additional sap output without dbx, including de-emphasis high integration level with automatically tuned integrated filters input level adjustment i 2 c-bus controlled alignment-free sap processing stereo pilot pll circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via i 2 c-bus automatic pilot cancellation composite input noise detector with i 2 c-bus selectable thresholds for stereo and sap off i 2 c-bus transceiver. general description the tda9850 is a bipolar-integrated btsc stereo/sap decoder (i 2 c-bus controlled) for application in tv sets, vcrs and multimedia. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cc supply voltage 8.5 9 9.5 v i cc supply current - 58 75 ma v comp(rms) input signal voltage (rms value) 100% modulation l + r; f i = 300 hz - 250 - mv v or(rms) ; v ol(rms) output signal voltage (rms value) 100% modulation l + r; f i = 300 hz - 500 - mv g la input level adjustment control - 3.5 - +4.0 db a cs stereo channel separation f l = 300 hz; f r = 3 khz 25 35 - db thd l,r total harmonic distortion l + r f i = 1 khz - 0.2 - % s/n signal-to-noise ratio 500 mv (rms) mono output signal ccir noise weighting filter (peak value) - 60 - db din noise weighting filter (rms value) - 73 - dba type number package name description version tda9850 sdip32 plastic shrink dual in-line package; 32 leads (400 mil) sot232-1 TDA9850T so32 plastic small outline package; 32 leads; body width 7.5 mm sot287-1
1995 jun 19 3 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 license information a license is required for the use of this product. for further information, please contact: company branch address that corporation licensing operations 734 forest st. marlborough, ma 01752 usa tel.: (508) 229-2500 fax: (508) 229-2590 tokyo of?ce 405 palm house, 1-20-2 honmachi shibuya-ku, tokyo 151 japan tel.: (03) 3378-0915 fax: (03) 3374-5191
1995 jun 19 4 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram o ok, full pagewidth composite baseband input + + c2 13 14 15 c5 16 q1 ceramic resonator 17 dematrix + mode select + c6 18 + c7 19 de-emphasis l+r l - r/sap outl outr 27 21 stereo decoder sap without dbx 23 c8 22 r1 c3 c4 logic, i 2 c- transceiver mad 28 7 stereo mono sap to audio processing 9 8 sda scl supply + c18 24 6 + c19 12 10 v ref v cap v cc sap demodulator + c16 5 c15 4 input level adjust + 11 c1 noise detector stereo/sap switch c17 26 tda9850 stereo adjust dbx + c14 3 c13 r3 r2 1 2 + 32 + 31 + 30 + 29 c12 c11 c10 c9 + 25 + 20 c l c r only during adjustment mha010 fig.1 block, application and test diagram.
1995 jun 19 5 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 component list electrolytic capacitors 20%; foil capacitors 10%; resistors 5%; unless otherwise speci?ed; see fig.1. component value type remark c1 10 m f electrolytic 63 v c2 470 nf foil c3 4.7 m f electrolytic 63 v c4 220 nf foil c5 10 m f electrolytic 63 v; i leak < 1.5 m a c6 4.7 m f electrolytic 63 v c7 4.7 m f electrolytic 63 v c8 15 nf foil c9 10 m f electrolytic 63 v 10% c10 10 m f electrolytic 63 v 10% c11 1 m f electrolytic 63 v c12 1 m f electrolytic 63 v c13 47 nf foil 5% c14 10 m f electrolytic 63 v c15 100 nf foil c16 4.7 m f electrolytic 63 v c17 100 nf foil c18 100 m f electrolytic 16 v c19 100 m f electrolytic 16 v cr 2.2 m f electrolytic 63 v cl 2.2 m f electrolytic 63 v r1 2.2 k w r2 8.2 k w 2% r3 160 w 2% q1 csb503f58 radial leads csb503jf958 alternative as smd
1995 jun 19 6 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 pinning symbol pin description veo 1 variable emphasis output for dbx vei 2 variable emphasis input for dbx c nr 3 capacitor noise reduction for dbx c m 4 capacitor mute for sap c dec 5 capacitor dc-decoupling for sap agnd 6 analog ground dgnd 7 digital ground sda 8 serial data input/output scl 9 serial clock input v cc 10 supply voltage (+9 v) comp 11 composite input signal v cap 12 capacitor for electronic ?ltering of supply c p1 13 capacitor for pilot detector c p2 14 capacitor for pilot detector c ph 15 capacitor for phase detector c adj 16 capacitor for ?lter adjustment cer 17 ceramic resonator c mo 18 capacitor dc-decoupling mono c ss 19 capacitor dc-decoupling stereo/sap c r 20 adjustment capacitor, right channel outr 21 output, right channel c sde 22 capacitor sap de-emphasis sap 23 sap output v ref 24 reference voltage 0.5 (v cc - 1.5 v) c l 25 adjustment capacitor, left channel c nd 26 noise detector capacitor outl 27 output, left channel mad 28 programmable address bit c tw 29 capacitor timing wideband for dbx c ts 30 capacitor timing spectral for dbx c w 31 capacitor wideband for dbx c s 32 capacitor spectral for dbx fig.2 pin configuration. f page tda9850 mha012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 veo c s c w c ts c tw c nd c sde c l c r c ss c mo v ref vei c nr c m c dec agnd outl sap outr cer mad dgnd sda scl v cc comp v cap c p1 c p2 c ph c adj
1995 jun 19 7 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 functional description input level adjustment the composite input signal is fed to the input level adjustment stage. the control range is from - 3.5 to +4.0 db in steps of 0.5 db. the subaddress control 4 of tables 5 and 6 and the level adjust setting of table 10 allows an optimum signal adjustment during the set alignment. the maximum input signal voltage is 2 v (rms). stereo decoder the output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 khz. the composite signal is then fed into a pilot detector/pilot cancellation circuit and into the mpx demodulator. the main l + r signal passes a 75 m s fixed de-emphasis filter and is fed into the dematrix circuit. the decoded sub-signal l - r is sent to the stereo/sap switch. to generate the pilot signal the stereo demodulator uses a pll circuit including a ceramic resonator. the stereo channel separation is adjusted by an automatic procedure to be performed during set production. for a detailed description see section adjustment procedure. the stereo identification can be read by the i 2 c-bus (see table 2). two different pilot thresholds (data sts = 1; sts = 0) can be selected via the i 2 c-bus (see table 14). sap demodulator the composite signal is fed from the output of the input level adjustment stage to the sap demodulator circuit through a 5f h band-pass filter. the demodulator level is automatically controlled. the sap demodulator includes an internal field strength detector that mutes the sap output in the event of insufficient signal conditions. the sap identification signal can be read by the i 2 c-bus (see table 2). noise detector the composite input noise increases with decreasing antenna signal. this makes it necessary to switch stereo or sap off at certain thresholds. these thresholds can be set via the i 2 c-bus. with st0 to st3 (see table 6) the stereo threshold can be selected and with sp0 to sp3 the sap threshold. a hysteresis can be achieved via software by making the threshold dependent of the identification bits stp and sapp (see table 2). mode selection the stereo/sap switch feeds either the l - r signal or the sap demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. table 8 shows the different switch modes provided at the output pins outr and outl. dbx decoder the dbx circuit includes all blocks required for the noise reduction system in accordance with the btsc system specification. the output signal is fed through a 73 m s fixed de-emphasis circuit to the dematrix block. sap output independent of the stereo/sap switch, the sap signal is also available at pin sap. at sap, the sap signal is not dbx decoded. the capacitor at sde provides a recommended de-emphasis (150 m s) at sap. integrated ?lters the filter functions necessary for stereo and sap demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. the required filter accuracy is attained by an automatic filter alignment circuit.
1995 jun 19 8 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 adjustment procedure c omposite input level adjustment feed in from fm demodulator the composite signal with 100% modulation (25 khz deviation) l + r; f i = 300 hz. set input level control via i 2 c-bus monitoring outl or outr (500 mv 20 mv). store the setting in a non-volatile memory. a utomatic adjustment procedure connect 2.2 m f capacitors from acr and acl to ground. composite input signal l = 300 hz, r = 3.1 khz, 14% modulation for each channel. mode selection setting bits: stereo = 1, sap = 0 (see table 8). start adjustment by transmission adj = 1 in register ali3. the decoder will align itself. after 1 second minimum stop alignment by transmitting adj = 0 in register ali3 read the alignment data by an i 2 c-bus read operation from alr1 and alr2 (see chapter i 2 c-bus protocol) and store it in a non-volatile memory. the alignment procedure overwrites the previous data stored in ali1 and ali2. the capacitors from acr and acl may be disconnected after alignment. m anual adjustment manual adjustment is necessary when no dual tone generator is available (e.g. for service). spectral and wideband data have to be set to 10000 (middle position for adjustment range) composite input l = 300 hz; 14% modulation adjust channel separation by varying wideband data composite input l = 3 khz; 14% modulation adjust channel separation by varying spectral data iterative spectral/wideband operation for optimum adjustment store data in non-volatile memory. after every power-on, the alignment data and the input level adjustment data must be loaded from the non-volatile memory. t iming current for release rate due to possible internal and external spreading, the timing current can be adjusted via i 2 c-bus, see table 9, as recommended by dbx.
1995 jun 19 9 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model (hbm): c = 100 pf; r = 1.5 k w ; v = 2 kv; charge device model: c = 200 pf; r = 0 w ; v = 300 v. thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage 0 10 v v vcap voltage of v cap to gnd 0 v cc v v veo voltage of veo to gnd 0 1 2 v cc v v sda voltage of sda to gnd 0 8.5 v v scl voltage of scl to gnd 0 8.5 v v n voltage of all other pins to gnd v cc 3 8.5 v 0 8.5 v v cc < 8.5 v 0 v cc v t amb operating ambient temperature t j < 125 c - 20 +70 c t stg storage temperature - 65 +150 c v es electrostatic handling hbm; note 1 symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air sot232-1 55 k/w sot287-1 68 k/w
1995 jun 19 10 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 requirements for the composite input signal to ensure correct system performance notes 1. low-ohmic preferred, otherwise the signal loss and spreading at comp, caused by z o and the composite input impedance (see chapter characteristics; row head input level adjustment control) must be taken into account. 2. in order to prevent clipping at over-modulation (maximum deviation in the btsc system for 100% modulation is 73 khz). 3. for example colour bar or flat field white; 100% video modulation. symbol parameter conditions min. typ. max. unit comp l+r(rms) composite input level for 100% modulation l + r (25 khz deviation); rms value; f i = 300 hz measured at comp 162 250 363 mv d comp composite input level spreading under operating conditions t amb = - 20 to +70 c; aging; power supply in?uence - 0.5 - +0.5 db z source source impedance note 1 - low-ohmic 5 k w f lf low frequency roll-off 25 khz deviation l + r; - 2db -- 5hz f hf high frequency roll-off 25 khz deviation l + r; - 2 db 100 -- khz thd l,r total harmonic distortion l + r f i = 1 khz; 25 khz deviation -- 0.5 % f i = 1 khz; 125 khz deviation; note 2 -- 1.5 % s/n signal-to-noise ratio l + r/noise ccir 468-2 weighted quasi peak; l + r; 25 khz deviation; f i = 1 khz; 75 m s de-emphasis critical picture modulation; note 3 44 -- db with sync only 54 -- db a sb side band suppression mono into unmodulated sap carrier; sap carrier/side band mono signal: 25 khz deviation, f i = 1 khz; side band: sap carrier frequency 1 khz 40 -- db a sp spectral spurious attenuation l + r/spurious 50 hz to 100 khz; mainly n f h ; no de-emphasis; l + r; 25 khz deviation, f = 1 khz as reference n = 1, 4, 5, 6 35 -- db n = 2, 3 26 -- db
1995 jun 19 11 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 characteristics all voltages are measured relative to gnd; v cc =9v; r s = 600 w ; r l =10k w ; ac-coupled; c l = 2.5 nf; f i = 1 khz; t amb = +25 c; see fig.1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cc supply voltage 8.5 9 9.5 v v ripple(p-p) allowed supply voltage ripple (peak-to-peak value) f i = 50 hz to 100 khz -- 100 mv i cc supply current - 58 75 ma v ref internal reference voltage at pin v ref - 3.7 - v a ct crosstalk between bus inputs and signal outputs notes 1 and 2 - 110 - db input level adjustment control g la input level adjustment control - 3.5 - +4.0 db g step step resolution - 0.5 - db v i(rms) maximum input voltage level (rms value) 2 -- v z i input impedance 29.5 35 40.5 k w stereo decoder mpx l+r input voltage level for 100% modulation l + r; 25 khz deviation (rms value) input level adjusted via i 2 c-bus (l + r; f i = 300 hz); monitoring outl or outr - 250 - mv mpx l - r input voltage level for 100% modulation l - r; 50 khz deviation (peak value) - 707 - mv mpx (max) maximum headroom for l + r, l, r f mod < 15 khz; thd < 15% 9 -- db mpx pilot nominal stereo pilot voltage level (rms value) - 50 - mv st on(rms) pilot threshold voltage stereo on (rms value) data sts = 1 -- 35 mv data sts = 0 -- 30 mv st off(rms) pilot threshold voltage stereo off (rms value) data sts = 1 15 -- mv data sts = 0 10 -- mv hys hysteresis - 2.5 - db out l+r output voltage level for 100% modulation l + r at outl, outr input level adjusted via i 2 c-bus (l + r; f i = 300 hz); monitoring outl or outr 480 500 520 mv
1995 jun 19 12 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 a cs stereo channel separation l/r aligned with dual tone 14% modulation for each channel; see section adjustment procedure f l = 300 hz; f r = 3 khz 25 35 - db f l = 300 hz; f r = 8 khz 20 30 - db f l = 300 hz; f r =10khz 15 25 - db f l, r l, r frequency response 14% modulation; f ref = 300 hz l or r f i =50hzto10khz - 3 -- db f i = 12 khz -- 3 - db thd l,r total harmonic distortion l, r modulation l or r 1% to 100%; f i = 1 khz - 0.2 1.0 % s/n signal-to-noise ratio mono mode; ccir 468-2 weighted; quasi peak; 500 mv output signal 50 60 - db stereo decoder, oscillator (vcxo); note 3 f o nominal vcxo output frequency (32f h ) with nominal ceramic resonator - 503.5 - khz f of spread of free-running frequency with nominal ceramic resonator 500.0 - 507.0 khz d f h capture range frequency (nominal pilot) 190 265 - hz sap demodulator; note 4 sap i(rms) nominal sap carrier input voltage level (rms value) 15 khz frequency deviation of intercarrier - 150 - mv sap on(rms) threshold voltage sap on (rms value) -- 68 mv sap off(rms) threshold voltage sap off (rms value) 28 -- mv sap hys hysteresis - 2 - db sap lev sap output voltage level at outl, outr mode selector in position sap/sap; f mod = 300 hz; 100% modulation - 500 - mv f res frequency response 14% modulation; 50 hz to 8 khz; f ref = 300 hz - 3 -- db thd total harmonic distortion f i = 1 khz - 0.5 2.0 % symbol parameter conditions min. typ. max. unit
1995 jun 19 13 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 sap output z o output impedance - 80 120 w v o dc output voltage - 0.5v cc - 1.5 - v r l output load resistance (ac-coupled) 5 -- k w c l output load capacitance -- 2.5 nf v o(rms) nominal output voltage (rms value) 150 m s de-emphasis see fig.3 outputs outl and outr v o(rms) nominal output voltage (rms value) 100% modulation - 500 - mv head o output headroom 9 -- db z o output impedance - 80 120 w v o dc output voltage 0.45v cc - 1.5 0.5v cc - 1.5 0.55v cc - 1.5 v r l output load resistance (ac-coupled) 5 -- k w c l output load capacitance -- 2.5 nf a ct crosstalk l, r into sap 100% modulation; f i = 1 khz; l or r; mode selector switched to sap/sap 50 75 - db crosstalk sap into l, r 100% modulation; f i = 1 khz; sap; mode selector switched to stereo 50 70 - db d v st-sap output voltage difference if switched from l, r to sap 250 hz to 6.3 khz -- 3db dbx noise reduction circuit t adj stereo adjustment time see section adjustment procedure -- 1s i s nominal timing current for nominal release rate of spectral rms detector i s can be measured at pin c ts via current meter connected to 1 2 v cc + 0.25 v - 24 -m a d i s spread of timing current - 15 - +15 % i s range timing current range 7 steps via i 2 c-bus - 30 - % i t timing current for release rate of wideband rms detector - 1 3 i s -m a rel rate nominal rms detector release rate nominal timing current and external capacitor values wideband - 125 - db/s spectral - 381 - db/s symbol parameter conditions min. typ. max. unit
1995 jun 19 14 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 notes to the characteristics 1. crosstalk: 2. the transmission contains: a) total initialization with mad and sad for volume and 11 data words, see also definition of characteristics b) clock frequency = 50 khz c) repetition burst rate = 400 hz d) maximum bus signal amplitude = 5 v (p-p). 3. the oscillator is designed to operate together with murata resonator csb503f58 or csb503jf958 as smd. change of the resonator supplier is possible, but the resonator speci?cation must be close to the speci?ed ones. 4. the internal sap carrier level is determined by the composite input level and the level adjustment gain. 5. when reset is active the smu-bit (sap mute) and the lmu-bit (outl, outr mute) is set and the i 2 c-bus receiver is in the reset position. 6. the ac characteristics are in accordance with the i 2 c-bus specification for standard mode (clock frequency maximum 100 khz). a higher frequency, up to 280 khz, can be used if all clock and data times are interpolated between standard mode (100 khz) and fast mode (400 khz) in accordance with the i 2 c-bus specification. information about the i 2 c-bus can be found in brochure i 2 c-bus and how to use it (order number 9398 393 40011). noise detector f 0 noise band-pass centre frequency composite input level 100 mv (rms) - 185 - khz q quality factor - 6 -- ster1, sap1 lowest noise threshold for stereo off respectively sap off (rms value; see tables 11 and 12) f i = 185 khz 17 24 34 mv ster16, sap16 highest noise threshold for stereo off respectively sap off (rms value) f i = 185 khz 210 290 400 mv d ster, d sap noise threshold step width f i = 185 khz 0 1.5 3 db power-on reset; note 5 v reset(sta) start of reset voltage increasing supply voltage -- 2.5 v decreasing supply voltage 4.2 5 5.8 v v reset(end) end of reset voltage increasing supply voltage 5.2 6 6.8 v digital part (i 2 c-bus pins); note 6 v ih high level input voltage 3 - 8.5 v v il low level input voltage - 0.3 - +1.5 v i ih high level input current - 10 - +10 m a i il low level input current - 10 - +10 m a v ol low level output voltage i il =3ma -- 0.4 v symbol parameter conditions min. typ. max. unit 20 log v bus(p-p) v o(rms) -------------------- -
1995 jun 19 15 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 i 2 c-bus protocol i 2 c-bus format to read (slave transmits data) table 1 explanation of i 2 c-bus format to read (slave transmits data) table 2 de?nition of the transmitted bytes after read condition table 3 function of the bits in table 2 the master generates an acknowledge when it has received the first data word, alr1, then the slave transmits the next data word alr2. the master next generates an acknowledge, then slave begins transmitting the first data word alr1, and so on until the master generates no acknowledge and transmits a stop condition. s slave address r/ w a data ma data p name description s start condition; generated by the master standard slave address (mad) 1011011 pin mad not connected pin programmable slave address 1011010 pin mad connected to ground r/ w 1 (read); generated by the master a acknowledge; generated by the slave data slave transmits an 8-bit data word ma acknowledge; generated by the master p stop condition; generated by the master function byte msb lsb d7 d6 d5 d4 d3 d2 d1 d0 alignment read 1 alr1 y sapp stp a14 a13 a12 a11 a10 alignment read 2 alr2 y sapp stp a24 a23 a22 a21 a20 bits function stp stereo pilot identification (stereo received = 1) sapp sap pilot identification (sap received = 1) a1x to a2x stereo alignment read data a1x for wideband expander a2x for spectral expander y indefinite
1995 jun 19 16 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 i 2 c-bus format to write (slave receives data) table 4 explanation of i 2 c-bus format to write (slave receives data) if more than 1 byte of data is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of table 5 is performed. table 5 subaddress second byte after mad table 6 de?nition of third byte, third byte after mad and sad s slave address r/ w a subaddress a data a p name description s start condition standard slave address (mad) 101 101 1 pin mad not connected pin programmable slave address 101 101 0 pin mad connected to ground r/ w 0 (write) a acknowledge; generated by the slave subaddress (sad) see table 5 data see table 6 p stop condition function register msb lsb d7 d6 d5 d4 d3 d2 d1 d0 control 1 con1 0 0 0 0 0 1 0 0 control 2 con2 0 0 0 0 0 1 0 1 control 3 con3 0 0 0 0 0 1 1 0 control 4 con4 0 0 0 0 0 1 1 1 alignment 1 ali1 0 0 0 0 1 0 0 0 alignment 2 ali2 0 0 0 0 1 0 0 1 alignment 3 ali3 0 0 0 0 1 0 1 0 function register msb lsb d7 d6 d5 d4 d3 d2 d1 d0 control 1 con1 0 0 0 0 st3 st2 st1 st0 control 2 con2 0 0 0 0 sp3 sp2 sp1 sp0 control 3 con3 sap stereo 0 smu lmu 0 0 0 control 4 con4 0 0 0 0 l3 l2 l1 l0 alignment 1 ali1 0 0 0 a14 a13 a12 a11 a10 alignment 2 ali2 sts 0 0 a24 a23 a22 a21 a20 alignment 3 ali3 adj 0 0 0 0 tc2 tc1 tc0
1995 jun 19 17 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 table 7 function of the bits in table 6 table 8 mode selection table 9 timing current setting bits function st0 to st3 noise threshold for stereo sp0 to sp3 noise threshold for sap stereo, sap mode selection lmu mute control outl and outr smu mute control sap l0 to l3 input level adjustment adj stereo adjustment on/off a1x to a2x stereo alignment data a1x for wideband expander a2x for spectral expander tc0 to tc2 timing current alignment data sts stereo level switch function mode at data transmission status internal switch, readable bits: stp, sapp setting bits outl outr stereo sap sap sap sap received 1 1 mute mute no sap received 1 1 left right stereo received 1 0 mono mono no stereo received 1 0 mono sap sap received 0 1 mono mute no sap received 0 1 mono mono independent 0 0 function i s range data tc2 tc1 tc0 +30% 1 0 0 +20% 1 0 1 +10% 1 1 1 nominal 0 1 1 - 10% 0 1 0 - 20% 0 0 1 - 30% 0 0 0
1995 jun 19 18 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 table 10 level adjust setting table 11 stereo noise threshold (ster) g l (db) data l3 l2 l1 l0 +4.0 1111 +3.5 1110 +3.0 1101 +2.5 1100 +2.0 1011 +1.5 1010 +1.0 1001 +0.5 1000 0.0 0111 - 0.5 0110 - 1.0 0101 - 1.5 0100 - 2.0 0011 - 2.5 0010 - 3.0 0001 - 3.5 0000 threshold data st3 st2 st1 st0 ster1 0000 ster2 0001 ster3 0010 ster4 0011 ster5 0100 ster6 0101 ster7 0110 ster8 0111 ster9 1000 ster10 1001 ster11 1010 ster12 1011 ster13 1100 ster14 1101 ster15 1110 ster16 1111 table 12 sap noise threshold (sap) table 13 adj bit setting table 14 sts bit setting (pilot threshold stereo on) table 15 mute setting threshold data sp3 sp2 sp1 sp0 sap1 0000 sap2 0001 sap3 0010 sap4 0011 sap5 0100 sap6 0101 sap7 0110 sap8 0111 sap9 1000 sap10 1001 sap11 1010 sap12 1011 sap13 1100 sap14 1101 sap15 1110 sap16 1111 function data stereo decoder operation mode 0 auto adjustment of channel separation 1 function data st on 35 mv 1 st on 30 mv 0 function data lmu function data smu forced mute at outr, outl 1 forced mute at sap 1 no forced mute at outr, outl 0 no forced mute at sap 0
1995 jun 19 19 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 table 16 alignment data for expander in read register alr1 and alr2 and in write register ali1 and ali2 function data d4 ax4 d3 ax3 d2 ax2 d1 ax1 d0 ax0 gain increase 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 nominal gain 10000 01111 gain decrease 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000
1995 jun 19 20 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 fig.3 voltage at sap output. 150 m s de-emphasis. (1) 100% modulation. (2) 14% modulation. (3) 1% modulation. handbook, full pagewidth 10 1 10 - 1 mha011 10 3 1 10 10 2 f i (khz) v sap (mv rms) (1) (2) (3)
1995 jun 19 21 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 internal pin configurations fig.4 pin 1; veo. mha013 1 v b fig.5 pin 2; vei. mha014 2 600 w v b fig.6 pin 3; c nr . mha015 3 10 k w 10 k w v b fig.7 pin 4; c m . mha016 4 v b fig.8 pin 5; c dec . mha017 5 20 k w 20 k w v b fig.9 pin 8; sda. mha018 8 1.8 k w
1995 jun 19 22 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 fig.10 pin 9; scl. mha019 9 1.8 k w fig.11 pin 10; v cc and pin 12; v cap . mha020 12 10 300 w 4.7 k w 200 w v b fig.12 pin 11; comp. mha021 11 30 k w v b fig.13 pin 13; c p1 . mha022 13 3.5 k w v b fig.14 pin 14; c p2 . mha023 14 8.5 k w 12 k w v b fig.15 pin 15; c ph. mha024 15 10 k w 10 k w v b
1995 jun 19 23 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 fig.16 pin 16; c adj . mha025 16 v b fig.17 pin 17; cer. mha026 17 3 k w v b fig.18 pin 18; c mo and pin 19; c ss . mha027 18 10 k w 10 k w v b fig.19 pin 20; c r and pin 25; c l . mha028 20 20 k w 20 k w v b fig.20 pin 21; outr and pin 27 outl. mha029 21 5 k w v b fig.21 pin 22; c sde . mha030 22 10 k w v b
1995 jun 19 24 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 fig.22 pin 23; sap. mha031 23 v b fig.23 pin 24; v ref . mha032 24 3.4 k w 3.4 k w v b fig.24 pin 26; c nd . mha033 26 30 k w v b fig.25 pin 28; mad. mha034 28 1.8 k w v b fig.26 pin 29; c tw and pin 30; c ts . mha035 29 v b fig.27 pin 31; c w and pin 32; c s . 4.6 k w mha036 31 v b
1995 jun 19 25 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot232-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 32 1 17 16 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip32: plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
1995 jun 19 26 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.10 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot287-1 (1) 0.012 0.004 0.096 0.086 0.02 0.01 0.050 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 q a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 95-01-25 97-05-22
1995 jun 19 27 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 soldering dip, sdip, hdip, dbs and sil introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these cases reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dip or wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. soldering so introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these cases reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally-opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at between 270 and 320 c.
1995 jun 19 28 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1995 jun 19 29 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 notes
1995 jun 19 30 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 notes
1995 jun 19 31 philips semiconductors preliminary speci?cation i 2 c-bus controlled btsc stereo/sap decoder tda9850 notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (358)0-615 800, fax. (358)0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., 15/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)480 6960/480 6009 india: philips india ltd, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)7640 000, fax. (01)7640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd40 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 533061/1500/01/pp32 date of release: 1995 jun 19 document order number: 9397 750 00176

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